Forschung

Object-Oriented DPR Framework

Introduction

Nowadays, two innovative future trends regarding hardware development and hardware description can be found. The first trend concerns the hardware itself. Modern Xilinx FPGAs provide the possibility to be reconfigured partially and dynamically - which is called dynamical partial reconfiguration (DPR). DPR means that parts of the hardware can be exchanged while the rest of the circuit is running untouched. This opens a huge field of new functionalities on FPGAs. Examples of applications which can be improved using DPR are video processing, low-power, automotive or packet filtering. Other technologies like dynamically reconfigurable processors or scrubbing are not even possible without DPR. Therefore, DPR is a powerful and promising technology. Unfortunately, it is still very challenging to use. Today, using DPR means struggling with architectural details of the used FPGAs and the according synthesis and implementation tools. A developer would focus most of the time on DPR and only a small part of the time on the implementation of the actual modules - of course that is the opposite of what hardware engineers want to do.
The second trend concerns the way hardware is described. The rapidly increasing complexity of hardware led to the usage of computer aided hardware design and to the development of hardware description languages (HDLs). Today, the most important HDLs are VHDL and Verilog. Although these HDLs already allow to describe hardware on a very high level, the developer still has to handle registers, clocks and clock domains. Using an HDL operating on the algorithmic level, this is not necessary any longer. Here, designs can be described exactly as they are in software languages like C, without the need to care about registers or clocks - which is called high level synthesis (HLS). Many hardware developing groups are looking forward to an HDL which operates on the algorithmic level, since this would come with a significant increase in productivity. The aim is to be able to translate common software algorithms to hardware in an efficient way. In that process, the highest challenge is to make use of the hardware's intrinsic parallelism.
Although both DPR and HLS are important future trends regarding hardware design, they develop quite independently. Today's software-to-hardware compilers focus on conventional hardware and therefore have to remove dynamic aspects such as the instantiation of calculating modules at runtime. Even object-oriented languages like SystemC do not support the dynamic instantiation of objects (that means the usage of new or delete outside of the constructor) for synthesis at all. On the other hand, DPR tools are working on the lowest possible layer regarding FPGAs: the bitfile level. This paper focuses on the design and the implementation of a Framework combining the two technologies, since this has the potential to kill two birds with one stone. Firstly, DPR can change the programming paradigm in future HDLs regarding dynamic instantiations. Dynamic parts would not have to be removed any longer but could be realized on the target FPGA using DPR. Secondly, a high-level language support of DPR technologies could help end its shadowy existence and turn it into a commonly used method.

 

The Framework

Our DPR Framework consists of a software-to-hardware compiler, an NoC also reliable for data buffering, a Merger, an adaptive Scheduler and a Java Emulator. The reconfigurable modules are described in a Java-like language called POL (Parallel Object Language). For testing and verification, the POL sources can be translated to Java. The Java Emulator is then able to execute these Java files, giving a developer a first and quick chance to verify the correctness of the program.
The POL sources can also be translated to VHDL. The generated VHDL files are plugged into a Network on Chip called CM (Communication Matrix). The CM is responsible for the data forwarding between the modules and for the data buffering. The Merger combines the generated VHDL files and the CM files and starts several XST (Xilinx Synthesis Tool) synthesis runs, until all required netlist files (called NGC files) are created. These files represent the functionality of the static area and the functionality of the reconfigurable modules. They are used as input files for Xilinx PlanAhead, which eventually does the DPR floorplanning and generates the (partial) bitfiles using the Xilinx ISE Early Access tools. The CM is controlled by a Scheduler running in software on the Virtex' PowerPC. It determines which reconfigurable module is loaded into which PRR (partially reconfigurable region) at which time. Since the Scheduler also runs on the target FPGA, the reconfiguration has to be done via the ICAP (Internal Configuration Access Port). Therefore, the generated design is a selfreconfiguring system.

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